This invention relates in general to semi-conductor integrated circuits design and more particularly to CMOS integrated circuits with dual gate oxide thickness transistors in advanced manufacturing technology.
CMOS technology has powered the revolution in computing capability due to the long trend of performance and density gains with scaling. The steady downscaling of CMOS device dimension has been the main stimulus to the growth of micro electronics and computer industry over the past two decades.
As the channel length scales down, the supply voltage and gate oxide thickness also scale down. The supply voltage must be reduced with scaling as the active power, which is proportional to the square of supply voltage, and electric field will exceed reasonable limits. A high electric field can lead to a number of deleterious effects that could impact chip reliability.
Examples are hot-carrier injection into the gate oxide and electromigration due to the increased current density.
At short channel lengths the phenomenon called the xe2x80x9cshort channel effectxe2x80x9d looms large. To keep the short channel effect under control gate oxide thickness is reduced nearly in proportion to channel length. A simple rule is that the gate oxide thickness needs to be about {fraction (1/50)} to {fraction (1/25)} of channel length. When this rule is applied in further down-scaling, the necessary reduction in gate oxide thickness eventually results in a thickness so small that it is vulnerable to quantum-mechanical tunneling which gives rise to gate leakage current that increases exponentially with decreasing oxide thickness as the oxide thickness is scaled down.
FIG. 1 shows the gate leakage current density (A/cm2) versus various gate oxide thicknesses (nm). It can be seen from plot 110 that the gate leakage current increases exponentially with decreasing gate oxide thickness. Increased leakage current causes undesired effects such as corrupted dynamic signals and increased standby power dissipation etc. Scaling of supply voltage reduces the voltage swing, which is detrimental to analog circuit performance in general.
FIG. 2 shows, a functional block 200. For the purposes of illustration an APS (Active Pixel Sensor) circuit is shown in this figure. This figure illustrates an APS (Active Pixel sensor) pixel and part of read out circuit 200 as a functional block. The circuit consists of source follower transistor 250, reset transistor 240, photo diode 260 and read out transistors 270 and 280. The maximum voltage on node Vin 210 is Vmax=Vddxe2x88x92Vt, where Vdd is the power supply voltage and Vt is the transistor threshold voltage of reset transistor 240. The minimum voltage on node Vin 210 is Vmin=Vdsat+Vt, where Vdsat is the overdrive voltage above the threshold voltage Vt. In this case, Vdsat=Vgsxe2x88x92Vt, where Vgs is the voltage difference between transistor gate and source. The typical value of Vdsat is 0.2V. Therefore the voltage swing at the node Vin 210,                     Vswing        =                  xe2x80x83                ⁢                  Vmax          -          Vmin                                        =                  xe2x80x83                ⁢                  Vdd          -                      2            ⁢            Vt                    -                      Vdsat            .                              
As the technology scales, Vdd and Vt (upto certain limit) scale approximately linearly with channel length which reduces the voltage swing. FIG. 3 shows the trend in values of Vdd, Vt and gate oxide thickness (tox) as the technology scales. The plot 310 depicts the drop in power supply voltage Vdd while the channel length decreases. The plot 320 depicts the drop in the threshold voltage Vt with the reduction in channel length. The plot 330 shows the drop in gate oxide thickness with the reduction in channel length.
The saturation voltage Vdsat generally remains constant and does not depend upon technology scaling. As Vdsat does not scale with technology, voltage swing reduces faster than linearly. FIG. 4 shows the simulated Vswing for the functional block under consideration.
As the technology scales down, the voltage swing reduces below acceptable levels and the resulting thin gate oxide layer causes high leakage currents, which causes further undesirable effects.
It would be an advance in the art to enable further dimensional downscaling of CMOS circuits while achieving acceptable performance characteristics such as a large voltage swing and low leakage currents.
In view of the above, it is an object of the invention to obtain acceptable voltage swings while permitting the device scaling in circuits made in CMOS technology.
It is another object of the invention to have reduced leakage currents resulting in acceptable performance in circuits made in CMOS technology.
Further objects and advantages will become apparent upon reading the following description of the invention and its various embodiments.
The present invention describes the use of thin and thick gate oxide transistors in a functional block of a CMOS circuit within the core of an integrated circuit chip. The functional block comprises a first transistor having a thick gate oxide and a second transistor having a thin gate oxide being placed at a predetermined distance from the first transistor, whereby restricting the functional block to a predetermined area.
In one embodiment, the predetermined distance between the thin and thick gate oxide transistors is chosen based on a transistor stability criterion. The distance between the thin and thick transistors generally depends on the minimum channel length of the CMOS technology used and the power supply voltage applied to the transistors.
The techniques of the invention can be used among others, in the functional blocks such as operational amplifiers, 3T DRAM cells and image sensor pixels. The functional block can be a part of an image sensing system, a communication system, a memory circuit, a multi-media system, an embedded system, a signal processing chip, an analog signal circuit and a mixed signal circuit.
In one embodiment, the functional block comprises at least one photosensitive element. Such functional block in one case forms part of a CMOS image sensor circuit. A photo diode or a photo gate could be used as the photosensitive element in the above described circuit.
In another embodiment of the invention, a high voltage source is connected to the thick oxide transistors and a low voltage source is connected to the thin oxide transistors. Alternatively, both thin and thick oxide transistors are connected to an identical voltage source.
The present invention also provides for a method of making a functional block using thin and thick oxide transistors for a CMOS circuit within the core of an IC chip. The method includes growing a first transistor, having a thick gate oxide and growing a second transistor having a thin oxide at a predetermined distance from the first transistor. In one embodiment, the transistor growth process is based on a first mask for the thick oxide transistors and a second mask for the thin oxide transistors. The transistor growth process can further include use of different masks for a LDD implantation.
The invention further includes the techniques for choosing a transistor in a functional block based on a gate leakage current threshold and/or a voltage swing threshold.